Design Optimization Techniques Evaluation for High Performance Parallel FIR Filters in FPGA

This paper presents synthesis results on a method to minimize the amount of hardware needed to implement a parallel digital finite impulse response (FIR) filters for hardwired (fixed coefficients) implementation targeted for high performance. The proposed method employ a combination of two approaches: first, the reduction of the coefficients to N-Power-of-Two (NPT) terms, where the maximum number of non-zero in each coefficient is taken as a constraint, followed by Common Subexpression Elimination (CSE) among multipliers. We present results for a range of different filter specifications, using Quartus II FPGA synthesis tool. We concluded that for FPGA applications, the NPT is a good approach, while CSE is worthless.